Test compression for circuits with multiple scan chains

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dc.contributor.authorNovák Ondřejcs
dc.contributor.authorJeníček Jiřícs
dc.contributor.authorRozkovec Martincs
dc.date.accessioned2018-09-25T12:06:07Z
dc.date.available2018-09-25T12:06:07Z
dc.date.issued2015-01-01cs
dc.format.extent6cs
dc.identifier.doi10.1109/LATW.2015.7102510
dc.identifier.isbn978-1-4673-6710-3cs
dc.identifier.urihttps://dspace.tul.cz/handle/15240/29995
dc.language.isoengcs
dc.publisherInstitute of Electrical and Electronics Engineerscs
dc.publisher.cityPuerto Vallarta; Mexicocs
dc.relation.ispartofseries1cs
dc.relation.urihttp://www.scopus.com/record/display.uri?eid=2-s2.0-84933545367&origin=resultslist&sort=plf-f&src=s&st1=Test Compression for Circuits with Multiple Scan Chains&st2=&sid=78DE9ACA07CFA6FF3C0DC1353B741796.y7ESLndDIsN8cE7qwvy6w:20&cs
dc.subjectASIC Testingcs
dc.subjectDesign For Testability in IC Designcs
dc.subjectLinear Finite State Machinescs
dc.subjectTest Application Time Reductioncs
dc.subjectTest Data Volume Compressioncs
dc.titleTest compression for circuits with multiple scan chainscs
local.citation.epageneuvedenocs
local.citation.spageneuvedenocs
local.identifier.publikace3428
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