Test compression for circuits with multiple scan chains

Date
2015
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers
Abstract
Description
Subject(s)
ASIC Testing, Design For Testability in IC Design, Linear Finite State Machines, Test Application Time Reduction, Test Data Volume Compression
Citation
Item identifier
https://dspace.tul.cz/handle/15240/29995
 https://doi.org/10.1109/LATW.2015.7102510
ISSN
ISBN
978-1-4673-6710-3
Collections