Test response compaction method with improved detection and diagnostic abilities
Loading...
Date
2017
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
This paper describes a test response compaction method that preserves diagnostic information and enables
performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops.
The T flip-flop signature chain can preserve the information about the positions of the erroneous test response
occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop
chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern
compaction scheme. The influence of multiple errors on detection and localization capability of the compaction
system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed,
the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The
scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time
are given for several benchmark circuits in the paper as well.
Description
Subject(s)
Design for testability (DFT), Scan-based test, Linear finite state machines
Citation
ISSN
2334-3133
ISBN
978-153860471-7