Test response compaction method with improved detection and diagnostic abilities

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dc.contributor.authorNovák Ondřejcs
dc.contributor.authorPlíva Zdeněkcs
dc.date.accessioned2020-06-06T05:48:38Z
dc.date.available07-06-2017en
dc.date.available2020-06-06T05:48:38Z
dc.date.issued2018cs
dc.date.updated27-08-2020en
dc.description.abstractThis paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.
dc.format.extent8cs
dc.identifier.doi10.1016/j.microrel.2017.10.016
dc.identifier.issn0026-2714cs
dc.identifier.urihttps://dspace.tul.cz/handle/15240/154935
dc.identifier.urihttps://www.sciencedirect.com/science/article/pii/S0026271417304924?via%3Dihub
dc.language.isoengcs
dc.publisherElsevier BVcs
dc.relation.ispartofMicroelectronics Reliabilityen
dc.relation.ispartofseries1cs
dc.relation.urihttps://api.elsevier.com/content/article/eid/1-s2.0-S0026271417304924cs
dc.riv.kontrolni-cislo192236861cs
dc.riv.specifikaceRIV/46747885:24220/18:00004392!RIV19-MSM-24220___cs
dc.subjectDesign for testability (DFT)cs
dc.subjectError diagnosiscs
dc.subjecttest-per-clockcs
dc.subjectLinear finite state machinescs
dc.subjectScan-based testcs
dc.subjectTest data compressioncs
dc.subjectTest response compactioncs
dc.titleTest response compaction method with improved detection and diagnostic abilitiesen
local.citation.epage249-256cs
local.citation.spage249-256cs
local.identifier.publikace4392
local.identifier.wok423891400030en
local.relation.issueJAcs
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