Decompressors using nonlinear codes
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Date
2020-07
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Volume Title
Publisher
ELSEVIER, RADARWEG 29, 1043 NX AMSTERDAM, NETHERLANDS
Abstract
Test patterns are usually transferred from the tester to the circuit under test in a compressed form as it minimizes test access mechanism bandwidth and transfer time. It was found that nonlinear binary codes could be used for encoding test patterns in a similar way as it is done using linear codes, and the compression efficiency may be higher. The key important characteristic of the nonlinear codes is that the maximum number of codeword bits may be higher than it is obtained for the linear code words while the number of individually specified bits is preserved. It causes better encoding parameters that can be found for the transformation of code words into a test pattern that can feed a circuit under test with a higher number of parallel scan chains. The decompressors placed on a circuit under test transform nonlinear binary code words into test patterns with the help of nonlinear combinational or sequential circuits. In this paper, we propose a relatively fast heuristics that can be used for finding the decompressor nonlinear function truth tables guaranteeing a required number of specified bits within a test pattern. We quantify the benefits and costs of such nonlinear decompressors and verify the benchmark circuit test pattern encoding efficiency.
Description
Subject(s)
Integrated circuit testing, Scan test data compression, Test data volume, Test application time, Nonlinear binary codes